EPEPS 2011: PANEL DISCUSSION

Key Challenges and Future Directions for Design & Analysis of High-Speed Electronic Packages and Interconnects

Time:

5:30 p.m. - 6:30 p.m.; Tuesday, October 25, 2011

Moderator:

Prof. Vikram Jandhyala, University of Washington, Seattle, USA

Panelists:

Dr. Dian Yang, GM & Senior VP of Product Mgmt., Apache Design

Dr. George A. Katopis, Distinguished Engineer Emeritus, IBM

Dr. Andreas Cangellaris, University of Illinois, Urbana-Champaign

Dr. Madhavan Swaminathan, Georgia Institute of Technology

Dr. Devan Iyer, Texas Instruments

Judy Priest, Cisco Systems, Inc.

Ken Willis, Sigrity, Inc.

Abstract: Preserving Signal and Power Integrity has become highly critical in modern electronic designs. Achieving accurate high-speed signaling using low-power designs and low-cost packaging is a key challenge facing system designers. To successfully reach this objective requires attention to circuit design, package design, analysis techniques as well as tools and a view towards emerging technologies for maintaining performance growth into the future. The panel will present expert opinions on the current/future of electronic interconnections, packages, systems as well as related design automation tools. Challenges in technology innovation, education, interoperability, and competition as related to the design and analysis of emerging electronic systems will also be discussed in an interactive format with audience participation.

Bio: Dr. Vikram Jandhyala is professor of electrical engineering at the University of Washington and director of the Applied Computational Engineering Lab. He is also founder and Chief Technologist at Nimbic, formerly Physware, a cloud-computing based electromagnetic simulation and electronic design automation startup. He chairs the professional masters program at UW EE. He is also a UW Presidential Entrepreneurial Faculty Fellow at UW's Center for Commericalization. Prof. Jandhyala's reserach interests encompass many aspects of large-scale simulation and physics-based computation. He is a recipient of several awards including the NSF CAREER award, Chair's award and Outstanding Research Advisor at UWEE, NASA Inventor Award, and graduate research awards from IEEE and the University of Illinois. He received his BTech in EE from IIT Delhi and his MS and PhD in EE from UIUC. He was a developer at Ansoft Corporation prior to joining UW in 2000. His research at UW has been funded by DARPA, NSF, SRC, Air Force, Navy, Lawrence Livermore, NASA, INTEL, the SBIR program, and several industrial grants.

Bio: Dr. Dian Yang serves as general manager and senior vice president of product management at Apache Design, Inc. - a wholly-owned subsidiary of ANSYS, Inc. Prior to joining Apache, Dr. Yang co-founded InnoLogic Systems, a provider of formal verification solutions for full-custom designs. After the acquisition of InnoLogic Systems by Synopsys, Dr. Yang continued to lead the adoption, integration, and advancement of the InnoLogic products as senior director in the implementation business unit. Prior to InnoLogic Systems, Dr. Yang held various management positions in Silicon Graphics, Inc., LSI Corporation, and Avant! Corporation. Dr. Yang has extensive experience in development and management of EDA software, including memory compilers, static timing tools, DFT and functional verification solutions. He received his M.S. and Ph.D. in computer science from Stanford University and a Bachelor of Science degree from Shanghai University of Science and Technology.

Bio: Dr. George Katopis is an IEEE Fellow, and Distinguished Engineer Emeritus of IBM Corp., where he worked for 35 years as a Large System Packaging Technology Strategist prior to his retirement. In this capacity, Mr. Katopis was involved with all high end systems' package designs produced by IBM Corp. during the last two decades. His field of expertise and interest is Signal Integrity and Switching Noise Containment where he holds dozen of US patents. He has co-authored over 100 conference papers and 3 book chapters during his career in subjects of his interest. The application of time domain analysis and the ultilization of multiple processor computation for the characterization of the performance of modern Serial buffers is his current focus area. He is a graduate of Columbia University with an MPh degree in 1974.

Bio: Dr. Andreas Cangellaris is M. E. Van Valkenburg Professor and Department Head in the Department of Electrical Engineering, at the University of Illinois, Urbana-Champaign. He has spent over twenty years in academia, first at the University of Arizona (1987-1997) and then at the University of Illinois (1997- to date). Professor Cangellaris' research interests include computational electromagnetics and teh development of modeling methodologies and tools for performance analysis and design of high-speed/high-frequency electronics systems and multi-physics devices. He is a Fellow of IEEE and serves as Editor of the IEEE Press Series on Electromagnetic Field Theory. He was one of the co-founders of the Ieee Topical Meeting on Electrical Performance of Electronic Packaging. Professor Cangellaris received the Alexander von Humboldt Research Award from Germany in 2005 for his contributions to engineering applications of electromagnetic field theory.

Bio: Dr. Madhavan Swaminathan is the Joseph M. Pettit Professor in Electronics in the School of Electrical and Computer Engineering, Georgia Tech, Director of the Interconnect and Packaging Center, Georgia Tech, and the Founder and CTO of E-System Design, a company focusing on the development of CAD tools for achieving signal and power integrity in integrated 3D micro and nano-systems. He is also the co-founder of Jacket Micro Devices, a company that specialized in integrated RF modules and substrates for wireless applications (acquired by AVX Corporation). He was formerly the Deputy Director of the Microsystems Packaging Research Center at Georgia Tech. Prio to joining Georgia Tech., he was with IBM working on packaging for supercomputers. He is the author of more than 325 journal and conference publications, holds 22 patents, is the author of 3 book chapters, and author and co-editor of 2 books. He is an IEEE Fellow. He received his M.S. and PhD in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.

Bio: Dr. Devan Iyer. As Director of Texas Instrument's Worldwide Semiconductor Packaging operations, Dr. Mahadevan "Devan" Iyer oversees a global team that drives a process to determine the packaging design and technologies that best meet the requirements of TI's customers in measures of miniaturization, performance, cycle time and cost. With more than 25 years of experience in microelectronics and packaging, Iyer is a recognized authority on packaging technologies. He has published more than 180 technical publications, has 28 patents to his credit and is a frequent invited speaker at industry meetings and conferences.

Bio: Judy Priest is a Cisco Distinguished Engineer and Engineering Manager in the Scalable Networks Group at Cisco Systems, Inc. She has been working in industry for over 25 years in the area of high speed signaling technology, circuit design, packaging and interconnect, and timing specification, in chip and system applications. She collaborates cross functionally with architects, design, marketing, and manufacturing for product optimization. Judy is a recognized industry expert and is frequently invited to speak at international electronics and packagin conferences, and has participated in several IEEE and JEDEC standards committees. Judy has previously worked at Digital Equipment Corporation, Hewlett Packard, Silicon Graphics, and Atheros Communications, as well as startup ventures.

Bio: Ken Willis is a Product Marketing Manager at Sigrity, responsible for advanced signal integrity solutions. He has more than 20 years of experience in the modeling, analysis, design, and fabrication of high-speed digital circuits. Prior to Sigrity, Ken held engineering, marketing, and management positions with Tyco, Compaq Computers, Sirocco Systems, Sycamore Networks, and Cadence Design Systems.